Semiconductors

Citations to U.S. patents by U.S. patents granted in 2023

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  1. (5) 15 9735131    Multi-stack package-on-package structures
  Inventors:  An-Jhih Su; Chen-Hua Yu

  *2. 9 6838718    Ferroelectric capacitor and ferroelectric memory
  Inventors:  Takashi Nakamura

  *3. 8 11545204    Non-linear polar material based memory bit-cell with multi-level storage by applying different voltage levels
  Inventors:  Rajeev Kumar Dokania; Noriyuki Sato; Tanay Gosavi; Pratyush Pandey; Debo Olaosebikan; Amrita Mathuriya; Sasikanth Manipatruni

  4. (1) 7 10263100    Buffer regions for blocking unwanted diffusion in nanosheet transistors
  Inventors:  Zhenxing Bi; Kangguo Cheng; Juntao Li; Peng Xu

  4. (5) 7 10535608    Multi-chip package structure having chip interconnection bridge which provides power connections between chip and package substrate
  Inventors:  Joshua Rubin; Lawrence A. Clevenger; Charles L. Arvin

  *4. 7 11538514    Writing scheme for 1TnC ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches on the plate-lines of the bit-cell
  Inventors:  Rajeev Kumar Dokania; Amrita Mathuriya; Sasikanth Manipatruni

  *4. 7 9548366    Self aligned contact scheme
  Inventors:  Tsai-Jung Ho; Kuang-Yuan Hsu; Pei-Ren Jeng

  *8. 6 10083863    Contact structure for semiconductor device
  Inventors:  Yun-Yu Hsieh; Jeng Chang Her; Cha-Hsin Chao; Yi-Wei Chiu; Li-Te Hsu; Ying Ting Hsia

  *8. 6 10170534    Display device
  Inventors:  Dongwook Kim; Wonkyu Kwak; Sunja Kwon; Seho Kim; Hansung Bae

  *8. 6 10256158    Insulated epitaxial structures in nanosheet complementary field effect transistors
  Inventors:  Julien Frougier; Ruilong Xie; Steven Bentley; Puneet H. Suvarna

  *8. 6 7397101    Germanium silicon heterostructure photodetectors
  Inventors:  Gianlorenzo Masini; Lawrence C. Gunn, III; Giovanni Capellini

  *8. 6 8841777    Bonded structure employing metal semiconductor alloy bonding
  Inventors:  Mukta G. Farooq; Zhengwen Li; Zhijiong Luo; Huilong Zhu

  *8. 6 9362355    Nanosheet MOSFET with full-height air-gap spacer
  Inventors:  Kangguo Cheng; Bruce B. Doris; Michael A. Guillorn; Xin Miao

  *8. 6 9607967    Multi-chip semiconductor package with via components and method for manufacturing the same
  Inventors:  Shing-Yih Shih

  *8. 6 9640531    Semiconductor device, structure and methods
  Inventors:  Zvi Or-Bach; Brian Cronquist

  *8. 6 9899515    Fabrication of a pair of vertical fin field effect transistors having a merged top source/drain
  Inventors:  Kangguo Cheng; Xin Miao; Wenyu Xu; Chen Zhang

  *8. 6 9991352    Methods of forming a nano-sheet transistor device with a thicker gate stack and the resulting device
  Inventors:  Julien Frougier; Ali Razavieh; Ruilong Xie; Steven Bentley

  1. (2) 480 9520482    Method of cutting metal gate
  Inventors:  Po-Chin Chang; Chih-Hao Wang; Kai-Chieh Yang; Shih-Ting Hung; Wei-Hao Wu; Gloria Wu; Inez Fu; Chia-Wei Su; Yi-Hsuan Hsiao

  2. (1) 479 9236267    Cut-mask patterning process for fin-like field effect transistor (FinFET) device
  Inventors:  Ho Wei De; Kuei-Liang Lu; Ming-Feng Shieh; Ching-Yu Chang

  2. (2) 479 9576814    Method of spacer patterning to form a target integrated circuit pattern
  Inventors:  Chieh-Han Wu; Cheng-Hsiung Tsai; Chung-Ju Lee; Ming-Feng Shieh; Ru-Gun Liu; Shau-Lin Shue; Tien-I Bao

  4. (4) 286 9372206    Testing of semiconductor chips with microbumps
  Inventors:  Wei-Cheng Wu; Hsien-Pin Hu; Shang-Yun Hou; Shin-puu Jeng; Chen-Hua Yu; Chao-Hsiang Yang

  4. (5) 286 9281254    Methods of forming integrated circuit package
  Inventors:  Chen-Hua Yu; Chi-Hsi Wu; Wen-Chih Chiou; Hsiang-Fan Lee; Shih-Peng Tai; Tang-Jung Chiu

  6. (5) 284 9496189    Stacked semiconductor devices and methods of forming same
  Inventors:  Chen-Hua Yu; Chien-Hsun Lee; Tsung-Ding Wang; Jung Wei Cheng

  7. (7) 235 9105490    Contact structure of semiconductor device
  Inventors:  Sung-Li Wang; Ding-Kang Shih; Chin-Hsiang Lin; Sey-Ping Sun; Clement Hsingjen Wann

  8. (8) 225 9236300    Contact plugs in SRAM cells and the method of forming the same
  Inventors:  Jhon-Jhy Liaw

  9. (10) 188 9608116    FINFETs with wrap-around silicide and method forming the same
  Inventors:  Kuo-Cheng Ching; Ching-Wei Tsai; Chi-Wen Liu; Chih-Hao Wang; Ying-Keung Leung

  10. (9) 174 8785285    Semiconductor devices and methods of manufacture thereof
  Inventors:  Ji-Yin Tsai; Yao-Tsung Huang; Chih-Hsin Ko; Clement Hsingjen Wann

Advanced Transistor Architectures: to overcome the limitations of traditional silicon-based devices.

• US Patent No. 10263100 ("Buffer regions for blocking unwanted diffusion in nanosheet transistors") by Bi et al. and US Patent No. 9362355 ("Cut-mask patterning process for fin-like field effect transistor (FinFET) device") by Ho et al. highlight the ongoing pursuit of smaller, faster, and more energy-efficient transistors, such as FinFETs and nanosheet transistors.


• US Patent No. 9899515 ("Fabrication of a pair of vertical fin field effect transistors having a merged top source/drain") by Cheng et al. and US Patent No. 9991352 ("Methods of forming a nano-sheet transistor device with a thicker gate stack and the resulting device") by Frougier et al. demonstrate advancements in transistor fabrication techniques, enabling improved performance and reliability.

• US Patent No. 9735131 ("Multi-stack package-on-package structures") by Su et al. and US Patent No. 10535608 ("Multi-chip package structure having chip interconnection bridge which provides power connections between chip and package substrate") by Rubin et al. highlight the importance of advanced packaging technologies for improving system performance, power efficiency, and density.

• US Patent No. 6838718 ("Ferroelectric capacitor and ferroelectric memory") by Nakamura and US Patent No. 11545204 ("Non-linear polar material based memory bit-cell with multi-level storage by applying different voltage levels") by Dokania et al. demonstrate the growing interest in ferroelectric memories and other emerging memory technologies for applications in high-performance computing and artificial intelligence.

• US Patent No. 9362355 ("Cut-mask patterning process for fin-like field effect transistor (FinFET) device") by De et al. and US Patent No. 9548303 ("FinFET devices with unique fin shape and the fabrication thereof") by Lee et al. demonstrate the ongoing refinement of FinFET fabrication techniques, enabling improved performance and reduced power consumption.


• US Patent No. 10263100 ("Buffer regions for blocking unwanted diffusion in nanosheet transistors") by Bi et al. and US Patent No. 10535608 ("Multi-chip package structure having chip interconnection bridge which provides power connections between chip and package substrate") by Rubin et al. highlight the exploration of next-generation transistor architectures, such as nanosheet transistors, for continued scaling and performance enhancement.

• US Patent No. 9735131 ("Multi-stack package-on-package structures") by Su et al. and US Patent No. 10535608 ("Multi-chip package structure having chip interconnection bridge which provides power connections between chip and package substrate") by Rubin et al. demonstrate the growing importance of advanced packaging techniques, such as 3D stacking, for achieving higher levels of integration and performance.

• US Patent No. 11545204 ("Non-linear polar material based memory bit-cell with multi-level storage by applying different voltage levels") by Dokania et al. and US Patent No. 11538514 ("Writing scheme for 1TnC ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches on the plate-lines of the bit-cell") by Dokania et al. highlight the exploration of emerging memory technologies, such as ferroelectric memories, for enhanced performance and energy efficiency.

Note: This article is based on the provided list of patents and may not be exhaustive.

#Semiconductors #FinFET #Transistors #3DIntegration #3DPackaging #Memory #AI #IoT #Innovation #IPStrategy #PatentAnalysis #TechnologyLaw #IntellectualProperty

References:
Raw data from: U.S. Patent and Trademark Office. "Data Download Tables." PatentsView. Accessed September 7, 2024. https://patentsview.org/download/data-download-tables.

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