(Weighted Score) Micro-Structural and Nano-Technology

Citations to U.S. patents by U.S. patents granted in 2024

Top 10   [Cited by Examiner | Cited by Applicant]

Related WIPO fields:[Semiconductors | Materials, metallurgy | Optics | Measurement | Basic materials chemistry | Electrical machinery, apparatus, energy | Computer technology All WIPO fields

[Cited by Examiner | Cited by Applicant]
Most Cited by Examiners

  1. Weighted Score: 5.000 10510620    Work function metal patterning for N-P space between active nanostructures
  Inventors: Daniel Chanemougame; Steven R. Soss; Steven Bentley; Julien Frougier; Ruilong Xie

  2. Weighted Score: 3.500 10170638    Nanosheet substrate isolated source/drain epitaxy by dual bottom spacer
  Inventors: Alexander Reznicek

  3. Weighted Score: 3.333 10825736    Nanosheet with selective dipole diffusion into high-k
  Inventors: Jingyun Zhang; Takashi Ando; Choonghyun Lee; Alexander Reznicek

  4. Weighted Score: 3.000 10879308    Stacked nanosheet 4T2R unit cell for neuromorphic computing
  Inventors: Takashi Ando; Bahman Hekmatshoartabari; Alexander Reznicek

  4. Weighted Score: 3.000 9947804    Methods of forming nanosheet transistor with dielectric isolation of source-drain regions and related structure
  Inventors: Julien Frougier; Min Gyu Sung; Ruilong Xie; Chanro Park; Steven Bentley

  6. Weighted Score: 2.500 10030186    Heat transfer medium
  Inventors: Ki CHAN

  6. Weighted Score: 2.500 10263100    Buffer regions for blocking unwanted diffusion in nanosheet transistors
  Inventors: Zhenxing Bi; Kangguo Cheng; Juntao Li; Peng Xu

  6. Weighted Score: 2.500 9954058    Self-aligned air gap spacer for nanosheet CMOS devices
  Inventors: Shogo Mochizuki; Alexander Reznicek; Joshua M. Rubin; Junli Wang

  9. Weighted Score: 2.167 6122973    Electrostatic capacity-type pressure sensor with reduced variation in reference capacitance
  Inventors: Kazuo Nomura; Kiyoshi Tanaka; Satoshi Nakao; Hideki Tanigami; Kazutaka Hayashi

  10. Weighted Score: 2.000 10109479    Method of making a semiconductor device with a buried insulating layer formed by annealing a superlattice
  Inventors: Robert J. Mears; Robert John Stephenson; Keith Doran Weeks; Nyles Wynn Cody; Marek Hytha

  10. Weighted Score: 2.000 10332803    Hybrid gate-all-around (GAA) field effect transistor (FET) structure and method of forming
  Inventors: Ruilong Xie; Edward J. Nowak; Bipul C. Paul; Steven R. Soss; Julien Frougier; Daniel Chanemougame; Lars Liebmann

  10. Weighted Score: 2.000 10666264    3D stacked integrated circuits having failure management
  Inventors: Tony M. Brewer

  10. Weighted Score: 2.000 10797163    Leakage control for gate-all-around field-effect transistor devices
  Inventors: Lan Yu; Heng Wu; Ruqiang Bao; Junli Wang; Dechao Guo

  10. Weighted Score: 2.000 10896956    Field effect transistor with reduced contact resistance
  Inventors: Remi Coquand; Shay Reboh

  10. Weighted Score: 2.000 10927294    Bright silver based quaternary nanostructures
  Inventors: Ashenafi Damtew Mamuye; Christopher Sunderland; Ilan Jen-La Plante; Chunming Wang; John J. Curley

  10. Weighted Score: 2.000 11545963    Ring oscillator-based Ising machine system
  Inventors: Kenneth M. Zick

  10. Weighted Score: 2.000 11674003    Nanocomposites
  Inventors: Peter D. Condo; David Scott Thompson

  10. Weighted Score: 2.000 4980308    Method of making a thin film transistor
  Inventors: Hisao Hayashi; Takeshi Matsushita

  10. Weighted Score: 2.000 5629951    Electrostatically-controlled cantilever apparatus for continuous tuning of the resonance wavelength of a fabry-perot cavity
  Inventors: Constance J. Chang-Hasnain; Edward C. Vail; Marianne S. Wu

  10. Weighted Score: 2.000 6652968    Pressure activated electrically conductive material
  Inventors: Dorothy H. J. Miller; Brian Miller

[Cited by Examiner | Cited by Applicant]
Most Cited by Applicants

  1. Weighted Score: 18.540 9520482    Method of cutting metal gate
  Inventors: Po-Chin Chang; Chih-Hao Wang; Kai-Chieh Yang; Shih-Ting Hung; Wei-Hao Wu; Gloria Wu; Inez Fu; Chia-Wei Su; Yi-Hsuan Hsiao

  2. Weighted Score: 18.440 9236267    Cut-mask patterning process for fin-like field effect transistor (FinFET) device
  Inventors: Ho Wei De; Kuei-Liang Lu; Ming-Feng Shieh; Ching-Yu Chang

  3. Weighted Score: 18.429 9576814    Method of spacer patterning to form a target integrated circuit pattern
  Inventors: Chieh-Han Wu; Cheng-Hsiung Tsai; Chung-Ju Lee; Ming-Feng Shieh; Ru-Gun Liu; Shau-Lin Shue; Tien-I Bao

  4. Weighted Score: 13.002 9608116    FINFETs with wrap-around silicide and method forming the same
  Inventors: Kuo-Cheng Ching; Ching-Wei Tsai; Chi-Wen Liu; Chih-Hao Wang; Ying-Keung Leung

  5. Weighted Score: 11.299 9502265    Vertical gate all around (VGAA) transistors and methods of forming the same
  Inventors: Ching-Hong Jiang; Li-Ting Wang; Teng-Chun Tsai; Shih-Chiang Chen

  6. Weighted Score: 11.171 9536738    Vertical gate all around (VGAA) devices and methods of manufacturing the same
  Inventors: Yu-Lien Huang; Chun-Hsiung Lin; Chi-Wen Liu

  7. Weighted Score: 9.881 9209247    Self-aligned wrapped-around structure
  Inventors: Jean-Pierre Colinge; Kuo-Cheng Ching; Ta-Pen Guo; Carlos H. Diaz

  8. Weighted Score: 9.281 9412817    Silicide regions in vertical gate all around (VGAA) devices and methods of forming same
  Inventors: Kai-Chieh Yang; Wai-Yi Lien

  8. Weighted Score: 9.281 9412828    Aligned gate-all-around structure
  Inventors: Kuo-Cheng Ching; Jean-Pierre Colinge; Zhiqiang Wu

  8. Weighted Score: 9.281 9472618    Nanowire field effect transistor device having a replacement gate
  Inventors: Richard Kenneth Oxland

 
 
References:
Raw data from: U.S. Patent and Trademark Office. "Data Download Tables." PatentsView. Accessed October 30, 2025. https://patentsview.org/download/data-download-tables.

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Published: April 7, 2026